第1 章 FPGA 架構(gòu)總體設(shè)計 ········································································· 1

1.1 FPGA 芯片研制流程·········································································· 1

1.2 FPGA 架構(gòu)設(shè)計流程·········································································· 7

1.3 FPGA 規(guī)模和資源劃分 ····································································· 17

1.4 FPGA 中功能模塊劃分 ····································································· 20

本章參考文獻(xiàn) ······················································································ 26

第2 章 FPGA 中時鐘網(wǎng)絡(luò) ·········································································· 30

2.1 簡介 ···························································································· 30

2.2 FPGA CDN 建模 ············································································· 33

2.3 時鐘網(wǎng)絡(luò)設(shè)計方法 ·········································································· 43

2.4 時鐘網(wǎng)絡(luò)的靈活性 ·········································································· 48

2.5 路由級聯(lián) ······················································································ 51

2.6 仿真實(shí)驗(yàn) ······················································································ 55

2.7 時鐘網(wǎng)絡(luò)熱學(xué)建模 ·········································································· 61

2.8 仿真實(shí)驗(yàn) ······················································································ 62

本章參考文獻(xiàn) ······················································································ 66

第3 章 FPGA 中電源/地線網(wǎng)絡(luò)和漏電流 ······················································· 68

3.1 電源/地線網(wǎng)絡(luò) ··············································································· 68

3.2 IR-DROP 分析與優(yōu)化 ········································································ 71

3.3 漏電流組成 ··················································································· 73

3.4 降低漏電流的方法 ·········································································· 74

3.5 基于VIA 分布的IR-DROP 分析 ··························································· 77

3.6 仿真實(shí)驗(yàn) ······················································································ 81

3.7 不均勻測試點(diǎn)的IR-DROP 求解 ··························································· 87

3.8 FPGA 電源網(wǎng)絡(luò)IR-DROP 分析 ···························································· 89

本章參考文獻(xiàn) ······················································································ 94

第4 章 FPGA 中可編程邏輯單元 ································································· 98

4.1 基于多路選擇器的邏輯單元 ······························································ 98

4.2 基于四輸入LUT 的可編程邏輯單元的設(shè)計 ·········································· 102

4.3 LUT 的模型與實(shí)現(xiàn) ········································································ 103

4.4 LUT 的輸入數(shù)目K 的確定 ······························································· 106

4.5 進(jìn)位邏輯 ····················································································· 109

4.6 基于查找表結(jié)構(gòu)的FPGA 的不足 ······················································· 115

4.7 AIC 結(jié)構(gòu)邏輯簇 ············································································ 117

4.8 基于AIC 結(jié)構(gòu)FPGA 的邏輯簇 ························································· 120

4.9 面向AIC 的映射工具及結(jié)構(gòu)評估平臺 ················································ 124

4.10 結(jié)構(gòu)特征匹配的AIC 簇互連優(yōu)化 ···················································· 125

4.11 仿真分析和比較 ·········································································· 131

本章參考文獻(xiàn) ····················································································· 133

第5 章 FPGA 中可編程I/O 模塊 ································································· 136

5.1 可編程I/O 系統(tǒng)結(jié)構(gòu) ······································································ 136

5.2 IOE 中的可編程輸入緩沖器設(shè)計 ······················································· 138

5.3 IOE 中的可編程輸出緩沖器設(shè)計 ······················································· 144

5.4 可編程I/O 的后端版圖設(shè)計······························································ 156

5.5 高可靠I/O 模塊的后端版圖與測試 ····················································· 166

5.6 可編程I/O 的供電策略 ··································································· 172

5.7 全芯片IO 的ESD 技術(shù) ··································································· 173

本章參考文獻(xiàn) ····················································································· 179

第6 章 FPGA 中DDR 存儲器接口 ······························································ 182

6.1 DDR SDRAM 芯片的工作原理 ·························································· 182

6.2 FPGA 芯片中DDR 存儲器接口系統(tǒng)設(shè)計 ············································· 184

6.3 DDR 存儲器接口控制器的設(shè)計和驗(yàn)證 ················································ 191

6.4 延時鎖相技術(shù) ··············································································· 194

6.5 延時鎖定環(huán)電路的分析與對比 ·························································· 196

6.6 數(shù)字延時鎖定環(huán)電路的性能分析與優(yōu)化 ·············································· 201

6.7 延時鎖定環(huán)線性模型與穩(wěn)定性分析 ···················································· 205

本章參考文獻(xiàn) ····················································································· 209

第7 章 FPGA 中數(shù)字延時鎖定環(huán) ································································ 213

7.1 實(shí)現(xiàn)相移的全數(shù)字延遲鎖定環(huán) ·························································· 213

7.2 數(shù)字控制延時鏈 ············································································ 215

7.3 時間數(shù)字轉(zhuǎn)換器 ············································································ 220

7.4 雙向移位計數(shù)器 ············································································ 221

7.5 鑒相器與鎖定邏輯 ········································································· 222

7.6 延遲鎖定環(huán)的版圖設(shè)計 ··································································· 224

7.7 延遲鎖定環(huán)環(huán)路的仿真 ··································································· 224

7.8 芯片的物理實(shí)現(xiàn)與測試平臺 ····························································· 225

7.9 DDR 接口的數(shù)據(jù)通路的測試驗(yàn)證 ······················································ 227

7.10 數(shù)字延時鎖定環(huán)的測試 ································································· 229

7.11 數(shù)字占空比矯正電路的測試 ···························································· 232

本章參考文獻(xiàn) ····················································································· 234

第8 章 FPGA 中連線連接盒 ······································································ 236

8.1 引言 ··························································································· 236

8.2 問題分析 ····················································································· 237

8.3 利用模擬退火算法優(yōu)化CB 拓?fù)浣Y(jié)構(gòu) ·················································· 241

8.4 實(shí)驗(yàn)及結(jié)果分析 ············································································ 246

8.5 連線開關(guān)盒的電路結(jié)構(gòu)設(shè)計方法 ······················································· 251

本章參考文獻(xiàn) ····················································································· 259

第9 章 FPGA 中互連線段長度分布 ····························································· 261

9.1 所提優(yōu)化方法的基本思路 ································································ 261

9.2 以面積延時積最小為目標(biāo)的優(yōu)化 ······················································· 265

9.3 針對所提優(yōu)化方法的討論 ································································ 268

9.4 設(shè)計實(shí)驗(yàn) ····················································································· 269

9.5 FPGA 芯片的設(shè)計實(shí)現(xiàn) ···································································· 270

9.6 芯片的測試準(zhǔn)備 ············································································ 272

本章參考文獻(xiàn) ····················································································· 275

第10 章 FPGA 中的配置模塊 ···································································· 277

10.1 配置系統(tǒng)的基本組成及特點(diǎn) ···························································· 277

10.2 配置系統(tǒng)的功能需求 ···································································· 279

10.3 配置系統(tǒng)的硬件結(jié)構(gòu)分析 ······························································ 281

10.4 配置碼流協(xié)議的結(jié)構(gòu)及其對配置系統(tǒng)的影響 ······································· 286

10.5 配置系統(tǒng)總體框架 ······································································· 292

10.6 配置碼流協(xié)議的設(shè)計 ···································································· 297

10.7 配置系統(tǒng)的電路設(shè)計與實(shí)現(xiàn) ···························································· 300

10.8 配置系統(tǒng)采用的驗(yàn)證工具與方法 ······················································ 305

10.9 配置系統(tǒng)的驗(yàn)證方案與功能點(diǎn)的抽取 ················································ 310

10.10 配置系統(tǒng)功能驗(yàn)證平臺的設(shè)計 ······················································· 312

10.11 配置系統(tǒng)驗(yàn)證結(jié)果 ······································································ 319

本章參考文獻(xiàn) ····················································································· 324

FPGA芯片架構(gòu)設(shè)計與實(shí)現(xiàn)造價信息

市場價 信息價 詢價
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（除稅）		 工程建議價
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杠鈴片架 3.0厚 查看價格 查看價格

達(dá)創(chuàng)

 件 13% 河北達(dá)創(chuàng)體育器材有限公司
杠鈴片架 3.0mm 查看價格 查看價格

達(dá)創(chuàng)

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杠鈴片架 61cm×58cm×124cm 查看價格 查看價格

39

 件 13% 河北達(dá)創(chuàng)體育器材有限公司
芯片卡 CA-EI-C品種:ID卡片; 查看價格 查看價格

霍尼韋爾

 個 13% 石家莊冠旭商貿(mào)有限公司
芯片卡 CA-MS-C品種:系統(tǒng)調(diào)試卡;型號:Mifare-1; 查看價格 查看價格

霍尼韋爾

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控制器組網(wǎng)芯片 查看價格 查看價格

套 13% 四川久遠(yuǎn)智能監(jiān)控有限責(zé)任公司昆明辦事
滴膠卡ID芯片 說明:100張起售 查看價格 查看價格

宏卡

 瓶 13% 沈陽宏卡科技開發(fā)有限公司
材料名稱 規(guī)格/型號 除稅
信息價		 含稅
信息價		 行情 品牌 單位 稅率 地區(qū)/時間
自動洗片機(jī) 查看價格 查看價格

臺班 韶關(guān)市2010年8月信息價
X光片脫水烘干機(jī) ZTH-340 查看價格 查看價格

臺班 韶關(guān)市2010年8月信息價
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價格 查看價格

臺班 汕頭市2011年3季度信息價
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價格 查看價格

臺班 汕頭市2011年2季度信息價
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臺班 廣州市2011年1季度信息價
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價格 查看價格

臺班 汕頭市2010年3季度信息價
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價格 查看價格

臺班 汕頭市2010年2季度信息價
彎管機(jī)(帶胎芯壓機(jī)) WC27-108 查看價格 查看價格

臺班 廣州市2010年1季度信息價
材料名稱 規(guī)格/需求量 報價數(shù) 最新報價
（元）		 供應(yīng)商 報價地區(qū) 最新報價時間
系統(tǒng)芯片 :(Vcc/Vdd)1.81V - 2V數(shù)據(jù)轉(zhuǎn)換器A/D: 16x12b振蕩器類型:內(nèi)部工作溫度:-40°C - 125°C(TA)|20個 1 查看價格 深圳市芯航國際電子有限公司 全國   2022-08-09
RFID芯片 工作頻率:915±45MHz|10600個 1 查看價格 深圳市奧斯達(dá)電子有限公司 全國   2018-08-21
信息芯片 DS1990A-F5|5926臺 1 查看價格 上海格瑞特科技實(shí)業(yè)有限公司 上海  上海市 2015-07-15
DSP芯片卡 1、DSP資源擴(kuò)展卡2、含2個DSP芯片3、處理芯片運(yùn)算能力不劣于800MHz|1塊 1 查看價格 廣州市熹尚科技設(shè)備有限公司 全國   2020-05-11
MI高頻芯片房卡 1.名稱:MI高頻芯片房卡2.參數(shù):M1高頻芯片卡,房卡智能化使用第十扇區(qū)|1000張 1 查看價格 全國  
儀表芯片 HY6264 稱重數(shù)據(jù)儲存|8163塊 1 查看價格 廣東華普電器實(shí)業(yè)集團(tuán)有限公司 廣東  佛山市 2015-11-10
儀表芯片 74HC573|8163塊 1 查看價格 廣東華普電器實(shí)業(yè)集團(tuán)有限公司 廣東  佛山市 2015-07-23
儀表芯片 TC7652CPD A/D運(yùn)放集成|8556塊 1 查看價格 廣東華普電器實(shí)業(yè)集團(tuán)有限公司 廣東  佛山市 2015-05-12

作 譯 者:余樂,謝元祿

出版時間:2017-07 千 字 數(shù):550

版 次:01-01 頁 數(shù):344

開 本:16開

I S B N :9787121306105

FPGA芯片架構(gòu)設(shè)計與實(shí)現(xiàn)常見問題

  • 什么是系統(tǒng)架構(gòu)設(shè)計?

    不同的架構(gòu)方法論，會將架構(gòu)分為不同視圖，每個視圖側(cè)重某一個方面、領(lǐng)域的問題。比如希賽推的ADMEMS架構(gòu)體系，分為以下幾種視圖：1. 數(shù)據(jù)架構(gòu)：描述數(shù)據(jù)的存儲結(jié)構(gòu)、格式等方面。2. 物理架構(gòu)：描述機(jī)器...

  • 什么是產(chǎn)品功能架構(gòu)設(shè)計

    產(chǎn)品功能架構(gòu)設(shè)計是從多種視角分析、設(shè)計，輸出架構(gòu)設(shè)計文檔，以實(shí)現(xiàn)產(chǎn)品的非功能屬性。

  • 用什么工具畫 軟件架構(gòu)設(shè)計圖

    　UIDesigner是騰訊用戶研究與體驗(yàn)設(shè)計部（CDC）設(shè)計研發(fā)的一款設(shè)計類軟件，打造一款可以讓設(shè)計師統(tǒng)一平臺和團(tuán)隊協(xié)作的平臺型設(shè)計工具，經(jīng)過1.0和2.0版本的經(jīng)驗(yàn)沉淀，我們決定對3.0版本進(jìn)行全...

FPGA芯片架構(gòu)設(shè)計與實(shí)現(xiàn)文獻(xiàn)

柜面量化考核系統(tǒng)三層架構(gòu)設(shè)計與實(shí)現(xiàn) 柜面量化考核系統(tǒng)三層架構(gòu)設(shè)計與實(shí)現(xiàn)

格式：pdf

大小：1.6MB

頁數(shù)： 6頁

評分： 4.5

為了提高柜面服務(wù)質(zhì)量和柜員的工作效率及工作積極性,降低差錯率,我們將柜員工作好壞與個人薪酬掛鉤,合理優(yōu)化、使用人力資源,避免出現(xiàn)"做好做差一個樣,做多做少一個樣"的不良現(xiàn)象。為此,公司人力資源部、業(yè)務(wù)管理部、信息技術(shù)部共同提出開發(fā)柜面量化考核系統(tǒng),通過量化柜員工作量和差錯率,實(shí)現(xiàn)績效考核與崗位工資發(fā)放相結(jié)合,工作

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模塊化可擴(kuò)展機(jī)群通信架構(gòu)設(shè)計與實(shí)現(xiàn) 模塊化可擴(kuò)展機(jī)群通信架構(gòu)設(shè)計與實(shí)現(xiàn)

格式：pdf

大?。?span id="tch4kia" class="single-tag-height">1.6MB

頁數(shù)： 2頁

評分： 4.8

當(dāng)前計算機(jī)機(jī)群得到廣泛應(yīng)用,文章分析了常規(guī)機(jī)群通訊框架的不足,提出了一種基于請求監(jiān)聽器、請求處理器和請求處理鏈的高可擴(kuò)展性機(jī)群通訊架構(gòu),并給出了具體實(shí)現(xiàn)。

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杜勇，四川省廣安市人，高級工程師。1999年于湖南大學(xué)獲電子工程專業(yè)學(xué)士學(xué)位，2005年于國防科技大學(xué)獲信息與通信工程專業(yè)碩士學(xué)位。主要從事數(shù)字信號處理、無線通信以及FPGA應(yīng)用技術(shù)研究。發(fā)表學(xué)術(shù)論文十余篇，出版《數(shù)字濾波器的MATLAB與FPGA實(shí)現(xiàn)（第2版）》、《數(shù)字通信同步技術(shù)的MATLAB與FPGA實(shí)現(xiàn)》、《數(shù)字調(diào)制解調(diào)技術(shù)的MATLAB與FPGA實(shí)現(xiàn)》等多部著作。

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本書從工程應(yīng)用的角度詳細(xì)闡述鎖相環(huán)技術(shù)的工作原理，利用MATLAB及System View仿真工具軟件討論典型電路的工作過程。以Altera公司的FPGA為開發(fā)平臺，以Verilog HDL語言為開發(fā)工具，詳細(xì)闡述鎖相環(huán)技術(shù)的FPGA實(shí)現(xiàn)原理、結(jié)構(gòu)、方法，以及仿真測試過程和具體技術(shù)細(xì)節(jié)，主要包括設(shè)計平臺及開發(fā)環(huán)境介紹、鎖相環(huán)跟蹤相位的原理、FPGA實(shí)現(xiàn)數(shù)字信號處理基礎(chǔ)、鎖相環(huán)路模型、一階環(huán)路的FPGA實(shí)現(xiàn)、環(huán)路濾波器與鎖相環(huán)特性、二階環(huán)路的FPGA實(shí)現(xiàn)、鎖相環(huán)路性能分析、鎖相測速測距的FPGA實(shí)現(xiàn) 。

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本書以Altera公司的FPGA器件為開發(fā)平臺，采用MATLAB及Verilog HDL語言開發(fā)工具，詳細(xì)闡述了數(shù)字濾波器的實(shí)現(xiàn)原理、結(jié)構(gòu)、方法及仿真測試過程，并通過大量工程實(shí)例分析其在FPGA實(shí)現(xiàn)過程中的具體技術(shù)細(xì)節(jié)。其主要內(nèi)容包括FIR濾波器、IIR濾波器、多速率濾波器、自適應(yīng)濾波器、變換域?yàn)V波器、解調(diào)系統(tǒng)的濾波器設(shè)計等。本書思路清晰、語言流暢、分析透徹，在簡明闡述設(shè)計原理的基礎(chǔ)上，追求對工程實(shí)踐的指導(dǎo)性，力求使讀者在較短的時間內(nèi)掌握數(shù)字濾波器的FPGA設(shè)計知識和技能。

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