FS2仿真器產(chǎn)品介紹

FS2仿真器ISA-ACTEL51

In-Target System Analyzer for

Actel Core8051? Microcontroller Core

ISA-ACTEL51專(zhuān)為 ACTEL51 設(shè)計(jì)，采用FS2公司獨(dú)有的 On-Chip Instrumentation（芯片級(jí)在線(xiàn)調(diào)試儀；OCI）和調(diào)試器，通過(guò)Actel 的FlashPro Lite 實(shí)現(xiàn)目標(biāo)連接，并具有四個(gè)硬件執(zhí)行斷點(diǎn)、無(wú)限的軟件斷點(diǎn)，以及可選的觸發(fā)器和追蹤功能。

FS2 產(chǎn)品與Actel 產(chǎn)品的緊密配合，能讓使用FS2 之 OCI 工具開(kāi)發(fā)以Actel Core8051 為基礎(chǔ) FPGA 系統(tǒng)的客戶(hù)，大幅縮短設(shè)計(jì)周期和降低開(kāi)發(fā)成本。Keil IDE 可與FS2 的工具完美結(jié)合。

特點(diǎn)

· 支持 bank switching

· 可讀寫(xiě)全部處理器寄存器, SFRs, program memory 和 data memory

· Go, halt processor run control

· 步執(zhí)行匯編或C 指令

· 無(wú)限制軟斷點(diǎn)設(shè)置

· 可下載 binary, Intel Hex或OMF51

· 可達(dá)4 硬件執(zhí)行斷點(diǎn)

· 跟蹤窗口可以顯示匯編、C或混合顯示

· 在源碼窗口中可設(shè)置、軟硬件斷點(diǎn)

Logic NavigatorTM for Actel FPGAs

Logic Analyzer and Debug Tool for Actel Programmable Logic

專(zhuān)為Actel FPGAs設(shè)計(jì)。

1、特點(diǎn)：

· 基于FS2 OCI技術(shù)跟蹤和觸發(fā)Actel FPGA 的信號(hào)分析

· 用戶(hù)可在Actel ProASIC, ProASIC(PLUS), MX, SX,和AX devices配置任意節(jié)點(diǎn)的邏輯分析

· 支持各個(gè)級(jí)別的觸發(fā)

· 可存儲(chǔ)出發(fā)條件

· 圖形化用戶(hù)界面可通過(guò)波形或文本輸出

· 命令行Tcl/tk 指令接口

· 可配置的跟蹤和觸發(fā)的優(yōu)化選擇

· 通過(guò) Actel FlashPro 或FlashPro Lite 和目標(biāo)板連接

· OCI 發(fā)生器迅速產(chǎn)生配置 OCI 邏輯塊選項(xiàng)并且可以產(chǎn)生實(shí)例代碼。

· 分析達(dá)4096個(gè)節(jié)點(diǎn)

· 可達(dá)32個(gè)可選的外部觸發(fā)接口

2、 System Navigator for Nios II

System Navigator Products for Nios II Embedded Processors

專(zhuān)為Nios II設(shè)計(jì)，采用FS2公司獨(dú)有的 On-Chip Instrumentation（芯片級(jí)在線(xiàn)調(diào)試儀；OCI）技術(shù)的調(diào)試器

特點(diǎn) Nios II套件 SNAV-NIOS II-USBProbe SNAV-NIOS II-ETHProbe ISA-NIOS II/T Probe

執(zhí)行斷點(diǎn)數(shù) 2 4 4 4

數(shù)據(jù)/周期斷點(diǎn) 2 4 4 4

跟蹤深度 16 frames Unlimited Unlimited Unlimited (on- chip)

128K frames (off-chip)

數(shù)據(jù)/總線(xiàn)周期跟蹤 No Yes Yes Yes

性能分析 No Yes Yes Yes

跟蹤時(shí)間標(biāo)記 No NO NO Yes

主機(jī)連接方式 USB 1.1 USB 2.0 USB 2.010/100 Ethernet USB 1.1 / EPP

觸發(fā) No NO NO Yes

目標(biāo)連接方式　 JTAG JTAG JTAG Mictor-38

離線(xiàn)跟蹤 No NO NO Yes

多核支持 No Yes Yes Yes3、 System Navigator for AMD Alchemy?　Processors

System Navigator tools for

AMD Alchemy Solutions Au1500? and Au1550? Processors

支持AMD芯片的獨(dú)特特點(diǎn)，對(duì)AMD Alchemy Au1500? 和 Au1550? 處理器深度跟蹤調(diào)試。擴(kuò)展調(diào)試支持 Windows 和 Linux下的 GDB/Insight調(diào)試。低成本下，優(yōu)秀的源碼級(jí)調(diào)試。同時(shí)也支持圖形界面下直觀方便的Mentor Graphics code|lab和XRAY debuggers 以及Viosoft embedded Linux Arriba 調(diào)試?？赏ㄟ^(guò)USB或網(wǎng)口與主機(jī)通訊。

特點(diǎn)：

利用OCI技術(shù)調(diào)試

·支持AMD Alchemy Au1500 和 Au1550 處理器和開(kāi)發(fā)板，也支持所有 MIPS 4K?, 4KE?, 4KS?, M4K?, 5K?, 20K?, 24K?, and 25K? cores

·支持多樣的源碼級(jí)調(diào)試環(huán)境

·通過(guò)SDBBP指令可以無(wú)限制設(shè)置斷點(diǎn)

·單步執(zhí)行匯編和C代碼

·讀寫(xiě)全部CPU寄存器

· 無(wú)論CPU停止或運(yùn)行都可讀寫(xiě)內(nèi)存

· MIPS標(biāo)準(zhǔn)的硬件斷點(diǎn)(EJTAG version 2.51 or later)

·支持FLASH 編程

·控制CPU運(yùn)行

·通過(guò)JTAG功能底層調(diào)試

·單線(xiàn)匯編和反匯編

·支持TCL./TK腳本語(yǔ)言的命令行接口

·包括MDI調(diào)試規(guī)范的2進(jìn)制軟件接口4、 System Navigator for AMD Geode?　GX and LX Processors

支持處理器：

AMD Geode? GX 466@0.9W processor

AMD Geode? GX 500@1.0W processor

AMD Geode? GX 533@1.1W processor

AMD Geode? LX 700@0.8W processor

AMD Geode? LX 800@0.9W processor

AMD Geode? LX 900@01.5W processor

特點(diǎn)：

·在 Geode GX和Geode LX 處理器利用On-Chip Instrumentation (OCI?) 調(diào)試擴(kuò)展

·讀寫(xiě)CPU 寄存器, MSRs, 內(nèi)存 和I/O

·控制CPU運(yùn)行

·單步執(zhí)行匯編指令

·無(wú)限的軟件斷點(diǎn)

·標(biāo)準(zhǔn)的片上跟蹤和可選的離片跟蹤

·片上跟蹤深度達(dá)128 x 64-bit幀

·離片跟蹤深度達(dá)64K x 64-bit 幀 (可選)

·支持系統(tǒng)管理模式,

·單步通過(guò)實(shí)模式到保護(hù)模式過(guò)渡直到監(jiān)控所有的所有寄存器更新

·支持Flash編程

·用調(diào)試寄存器執(zhí)行硬件斷點(diǎn)

·可在觸發(fā)窗口設(shè)置復(fù)雜觸發(fā)

·復(fù)雜觸發(fā)可監(jiān)控地址和周期類(lèi)型

·單行匯編和反匯編

·跟蹤窗口全面執(zhí)行跟蹤

·源碼窗口可執(zhí)行: go; halt; goto cursor; step over/into call

·源碼窗口下能夠設(shè)置和清除軟硬件斷點(diǎn)

·包括GNU-based GDB 源碼級(jí)程序調(diào)試

· Windows CE Platform Builder 和 在 Windows XP/XPE WinDbg 內(nèi)核級(jí)調(diào)試

·支持TCL./TK腳本語(yǔ)言的命令行接口5、System Navigator for Turbo 186 Cores：　System Navigator tools for VAutomation Turbo186 Core and

Lantronix DSTni-LX / DSTni-EX Processors

低成本下，優(yōu)秀的源碼級(jí)調(diào)試工具?？蛇x的圖形化界面，直觀方便。可通過(guò)USB或網(wǎng)口與主機(jī)通訊。

特點(diǎn)：

· 控制CPU運(yùn)行

· 單步執(zhí)行匯編指令

· 無(wú)限的軟件斷點(diǎn)

· 支持Flash編程

· 用調(diào)試寄存器執(zhí)行硬件斷點(diǎn)

· 支持C或匯編語(yǔ)言

· 源碼窗口能夠顯示C語(yǔ)言或混合顯示

· 源碼窗口可提供運(yùn)行控制

· 源碼窗口能夠設(shè)置或清除軟硬件斷點(diǎn)

· 源碼窗口允許選擇全局或局部變量并增加到變量窗口中

· 觸發(fā)窗口可設(shè)置復(fù)雜觸發(fā)

· 標(biāo)準(zhǔn)TCL./TK腳本語(yǔ)言的命令行接口

System Navigator for MIPS：

System Navigator tools for

MIPS Technologies MIPS32? and MIPS64? Cores

提供很多功能例如硬件觸發(fā)器、跟蹤邏輯分析在線(xiàn)仿真。

通過(guò)14針EJTAG連接目標(biāo)板，可通過(guò)網(wǎng)口、和usb.或并口連接主機(jī)，支持Mdi源碼級(jí)調(diào)試

軟件斷點(diǎn)

硬件事件識(shí)別

Mips芯片包含可配置硬件斷點(diǎn)的，可達(dá)到15個(gè)指令斷點(diǎn)執(zhí)行虛擬地址的識(shí)別。

只有當(dāng)特殊事件被激活，所有的斷點(diǎn)都可以禁止被Asid打破的斷點(diǎn)。觸發(fā)事件可以用于跟蹤的篩選。

靈活的內(nèi)外部程序和數(shù)據(jù)的選擇

跟蹤可以在片上或片下捕獲。內(nèi)部跟蹤深度可以從16到16k字節(jié)。當(dāng)源碼只有程序分支被存儲(chǔ)

特點(diǎn)

利用OCI技術(shù)調(diào)試

支持mips芯片

支持基于mips sde 工具鏈的gun,mentor 圖形開(kāi)發(fā)工具和xray以及voisoft

要求ejtag2.5 或以上

標(biāo)準(zhǔn)的片上跟蹤和離片跟蹤

片上跟蹤深度可達(dá)1M64BIT字

實(shí)時(shí)的PC執(zhí)行跟蹤載入、存儲(chǔ)地址，和數(shù)據(jù)跟蹤

通過(guò)觸發(fā)器可以切換跟蹤狀態(tài)

Off-chip trace up to 64K 64-bit words

通過(guò)SDBBP指令可以無(wú)限制設(shè)置斷點(diǎn)

單步執(zhí)行匯編和C代碼

讀寫(xiě)全部CPU和CP0寄存器

支持MIPS標(biāo)準(zhǔn)的硬件斷點(diǎn)

支持FLASH 編程

支持多核

控制CPU運(yùn)行

底層調(diào)試通過(guò)JTAG功能

單線(xiàn)匯編和反匯編

支持TCL./TK腳本語(yǔ)言的命令行接口

包括MDI調(diào)試規(guī)范的2進(jìn)制軟件接口

源碼級(jí)調(diào)試直觀易用

FS2仿真器Navigator IDE for MIPS：

Eclipse-based Navigator debugger IDE for

MIPS Technologies MIPS32? and MIPS64? Cores

與Eclipse兼容的圖形化MIPS核開(kāi)發(fā)調(diào)試環(huán)境8、ABS of the Benefits of MIPS PDtrace?

FS2 System Navigator JTAG ProbesMIPS? Software Toolkit

MIPS? SDE GNU based toolchain, MIPSsim(TM) Instruction Set Simulator,

MIPS? DSP Library and Technical Support

System Navigator for CAST8051

System Navigator tools for

CAST 8051 Synthesizable Microcontroller Cores

支持CPU:

（CAST R8051XC, R80515, R8051, C8051 cores）

兼容開(kāi)發(fā)環(huán)境

Keil μVision3 software

12、SNAV-HT80C51

System Navigator tools for Handshake Solutions

HT80C51 and HT80C51MX Clockless Microcontroller Cores

支持CPU: HT80C51 和 HT80C51MX

兼容開(kāi)發(fā)環(huán)境：Keil 系列

System Navigator for Mentor M8051EW

System Navigator tools for Mentor M8051EW

Synthesizable Microcontroller Cores

System Navigator for Philips LPC952

System Navigator for

Philips LPC952 Microcontroller

FS2仿真器ISA-JAZZ System Analyzer

In-Target System Analyzer for Improv Systems Jazz DSP Processor Cores

The ISA-JAZZ In-Target System Analyzer is designed to support the special features and integrated peripherals of the Jazz processor family. It works with the Improv Systems Jazz Standard Tool Suite and provides a JTAG interface to the family DSP processors.

The ISA-Jazz System Analyzer supports JTAG-based debugging for Improv Systems Jazz cores with COOL-Jazz debugging extensions. It features complete run control over one or more Jazz DSP processor cores and enables you to access and modify registers, memory, and I/O. The JTAG based probe works with the Improv Systems tool suite debugger for a graphical user interface. This provides a powerful multi core debug tool for Jazz cores with advanced features at a competitive price.

Key Features

· Read-write all processor registers, memory, and I/O ports

· Go and halt processor run control

· Single step by assembly or C source instruction

· Set hardware and software breakpoints

· Load binary, hex, S-records file formats

· Supports multiple Jazz cores on JTAG chain

· Supports flash programming

· Trigger-in/out signals

· Supported by Jazz debugger and development tool suite

FS2仿真器ISA-ZSP500

In-Target System Analyzer for LSI Logic ZSP500 DSP Core

The In-Target System Analyzer supports the LSI Logic ZSP?500 synthesizable DSP core. To learn more about the ZSP500 core, visit the web site at www.zsp.comThe ZSP500 core is available with optional FS2 On-chip Instrumentation (OCI?) IP with trace and triggering features for faster system debug and testing. It provides unique performance analysis features that make it easier to find execution bottlenecks and improve performance.

The FS2 system analyzer probe connects to the ZSP500 target system using a 14-pin JTAG connector or 38-pin Mictor cable (with off-chip trace system). The system runs on a Windows?98/NT/2000/XP PC over an IEEE-1284 EPP/bi-directional parallel port.

Key Features

· Supports LSI Logic ZSP500 DSP core

· Features FS2 On-Chip Instrumentation (OCI) technology

· On-chip trace (standard), off-chip trace, or both

· Supports 24-bit addressing

· Real-time PC execution trace

· Load/store address trace

· Detailed Execution Profiling Trace mode for measuring CPU resource utilization

· Point-to-point timing to assist in code performance optimization

· Trace can be gated on/off by on-chip triggers

· Scalable internal trace depth

· External trace port width and speed selectable

· Max trace depth: on-chip 1024 x 64-bit words, off-chip 64K x 64-bit words

· Unlimited software breakpoints

· ZSP hardware breakpoints

· Go, halt processor run control

· Read-write all general registers and control registers

· Supports multiple cores and mixed RISC/DSP development

· Host binary software interface adheres to MDI specification

· Command-line interface window with Tcl scripting

FS2仿真器Sitka Development Board

Evaluation and Development Board for Synopsys DesignWare PCI Express IP

The Sitka development and evaluation board was jointly developed by Synopsys and First Silicon Solutions for the Synopsys DesignWare PCI Express IP. The board functions as a standard PCIe add-in card for systems running either the Windows or Linux operating systems.

The Sitka board contains two large Xilinx Virtex-4 FPGA's which allow you to combine your design with the DesignWare PCI Express IP enabling you to test and debug your PCI Express application in hardware. The FPGA's support partitioning of large designs by providing 272 I/O pins between the two FPGA's. These I/O's can be configured for operation up to 1Gpbs point-to-point to provide high throughput data transfers or grouped into sets of unidirectional channels. The FPGA's are configured with on-board ROM that can hold two or more configurations depending on the bitfile compression that is used.

The board enables testing the DesignWare PCI Express IP with multiple PHYs for maximum flexibility in choosing the PHY for the final design. For testing purposes, you can use the built-in FX60 PHY connecting directly to specific connectors like the PCIe interface and SATA drives or through the 360-pin expansion connector. In addition to using the built-in FPGA PHYs, you can use daughter cards connected to the Sitka board via two different connector locations, including the PCI Express Standard PIPE_C (PHY Interface PCI Express Architecture Connector). The Sikta board can run any combination or all of these interfaces simultaneously.

The Sitka board, when used in conjunction with the industry standard DesignWare PCI Express IP enables faster and easier verification of the design in hardware.

Key Features

· PCIe x8 board edge connector (adaptors plug into a PCIe x1 or x4 PC slot)

· PCI Express PHY Interface for PCI Express Architecture Connector (PIPE_C) enables PHY testing through a PHY daughter card

· PMA Interface connector for use with Synopsys PHY daughter cards

· 2 SATA drive connectors

· 2 SFP connector sites for Gigabit Ethernet (GigE)

· 2 XENPAK connector sites for XAUI (adaptors for additional SATA or SFP)

· Cup connectors for TI power source modules

· 2 Xilinx JTAG connectors, one each wired to FX60 and LX100 for using the ChipScope Pro debugger

· Xilinx XC4VFX60-10FF1152

· Xilinx XC4VLX100-10FF1513

· 3 XCF32P configurable FLASH devices for 2 selectable Xilinx image loads

· 2 independent Xilinx-approved clock sources for the Rocket IO (PCIe and SATA)

· 2 clock sources for PMA PHY 'H' connector daughter card

· LEDs for board diagnostics

ISA-QMIPS

ISA-Eclipse

FS2 System Analyzers for

QuickLogic? QuickMIPS? ESP Family and

Eclipse? FPGA Devices

ISA-eZ80

In-Target System Analyzer for ZiLOG eZ80 Processor Family

The ISA-eZ80 In-Target System Analyzer is designed to support the special features and integrated peripherals of the eZ80 processor family. It supports the ZiLOG Developer Studio (ZDS) and is integrated with the IAR Embedded Workbench software tools to maximize your productivity.

The system analyzer features complete run control over the eZ80 processor and enables you to access and modify CPU registers, memory, and I/O. FS2's On-Chip Instrumentation (OCI(TM)) debug features built-in to the ZiLOG processors allow FS2 to provide a powerful debug tool with advanced features at a competitive price.

The ISA-eZ80 debugger hardware is contained in a compact chassis that connects to the target system using a 14-pin JTAG connector. The system runs on a Windows? 98/NT/2000 PC over an IEEE-1284 EPP/ECP high-speed parallel port or USB port. The JTAG target interface and high-speed parallel host intface provides typical 8K bytes/sec. loading speeds so you spend more time debugging than waiting for programs to load. A graphical, source level debugger program provides an intuitive, easy to use interface for use with the ZiLOG Developer Studio (ZDS) tools. The system can also be used with the IAR Embedded Workbench debugger interface (sold separately) for complete compatibility with IAR software tools.

IAR Embedded Workbench Interface

IAR Web site

Zilog Web site

Key Features

· Supports ZiLOG eZ80L92, eZ80F91, eZ80F92, eZ80F93, and other processors with available JTAG debug interface

· Read-write all processor registers, memory, and I/O

· Go and halt processor run control

· Trace window with executed assembly and source code

· Single step by assembly or C source instruction

· Unlimited software breakpoints

· Load binary, hex, S-records or COFF (from ZDS) and IAR file formats

· JTAG target and EPP parallel host interface for faster loading

· Flash programming support

· 4 hardware execution breakpoints

· 4 ZDI triggers monitor addrss, address ranges, with option to break on any cycle type

· 4 additional advanced hardware triggers on address, data value, and cycle types, with ranges and masking supported

· Trigger-in/out signals

· Single line assembler and disassembler

· Load code and debug symbols including code, variables, and variable types

· Source level debug from IAR Embedded Workbench interface

· Standalone source debug interface (GUI) supports ZDS tools

FLASH PRO OEM product for Actel ProASIC and ProASICPLUS devices

FPGAView? Software

Software for Configuring and Debugging Altera and Xilinx FPGA Devices with Tektronix Logic Analyzers

The FPGAView? software is a PC Windows-based program

FS2 BUS NAVIGATOR?

On-chip FS2 Bus Navigator? Solutions for AMBA, OCP,

and Sonics SiliconBackplane Bus Systems

The FS2 Bus Navigator? is used for monitoring signal activity and for debugging complex bus/system interactions in System-on-Chip designs. It allows the user to capture bus activity in real-time and display critical information for analysis on a host PC.

The system consists of an On-chip Instrumentation (OCI?) synthesizable logic block, a JTAG hardware probe, and PC based software for controlling probing and analysis. The OCI passively captures bus activity, buffers it using on-chip RAM, and transfers the collected data off-chip via a JTAG port to the external JTAG probe. The host PC controls the trace collection process and provides captured bus history to the user with an easy-to-use graphical interface. The system runs on a Windows? 2000/XP PC over a USB 2.0 or optional 10/100 Ethernet port. It provides a comprehensive debug tool for complex SoC bus designs at a competitive price.

Key Features

· Captures bus activity in real-time

· Available for AMBA, OCP, and Sonics SiliconBackplane buses

· Captures bus signals and additional user-defined inputs attached to other nodes in the SOC

· Bus clock mode trace stores signals on every clock

· Bus transfer mode aligns bus transfers and response phases for single event triggering using combinations of address, data, and control

· Filtering of wait and idle state cycles in bus transfer mode

· Trace storage qualifiers; single cycle, start or stop trace on any trigger, counter, and state sequencer condition

· Configurable for user defined number of Masters

· Trace buffer stores bus cycles or bus transfers based on RAM memory size

· Up to 16 user defined triggers recognize combinations of 1, 0, X, signal values

· Sequential event monitoring using cascadable trigger states (2 to 16 states)

· Two 32-bit event counter/timers

· Trigger conditions include bus and user defined signals, Event counter/timer value, and Trigger state

· Actions include Trigger, Trace control (start, stop, single), Trig Out control (pulse, assert, negate), Counter control (increment, start, stop, clear), and Goto state

· Trigger position variable in 1/512 increments of trace depth

· User difinable timestamp records duration of each trace frame from the start of trace, displayable as absolute or delta times

· Automatic trace clock frequency measurement allows displaying frame durations in either nanoseconds or clocks

· Multiple external trigger in/out with configurable logic levels

· Easy-to-use graphical software interface with state views and waveform views of data

· Symbolic lookup and signal value naming support for ease of viewing and analysis

· Optional VCD format export for integration with simulation environments

Cadence Emulation Tools Support

Integrating Instrumentation Tools into System-Level Verification Flows. This is a PowerPoint presentation.2100433B

位于美國(guó)俄勒岡州Lake Oswego的First Silicon Solutions(FS2)的公司是MIPS Technologies全資子公司。FS2公司專(zhuān)門(mén)致力于芯片知識(shí)產(chǎn)權(quán)(IP)、設(shè)計(jì)服務(wù)和針對(duì)SoC、SOPC、FPGA、ASSP和ASIC器件的編程、測(cè)試、調(diào)試和嵌入式跟蹤片上儀器(OCI)的開(kāi)發(fā)工具。

FS2公司的OCI技術(shù)可提供深度的、針對(duì)SoC內(nèi)部工作的、覆蓋整個(gè)系統(tǒng)的能見(jiàn)度，是實(shí)現(xiàn)成功設(shè)計(jì)和加速上市的關(guān)鍵。FS2從1999年起就與MIPS Technologies及其客戶(hù)密切合作，針對(duì)MIPS-Based(tm)核心，開(kāi)發(fā)尖端的系統(tǒng)除錯(cuò)與程序追蹤技術(shù)。這項(xiàng)合作關(guān)系后來(lái)更延伸至PDtrace(tm)（Program and Data Trace）芯片內(nèi)部與外部的追蹤系統(tǒng)開(kāi)發(fā)，并應(yīng)用在MIPS32(r) 4KE(tm)、MIPS32 24K(r)、以及MIPS32 24KE(tm)等系列的處理器核心。

此外，F(xiàn)S2還推出System Navigator以協(xié)助業(yè)者針對(duì)系統(tǒng)進(jìn)行開(kāi)發(fā)與除錯(cuò)，同時(shí)FS2亦提供Logic Navigator(tm)系列IP方案與相關(guān)工具，針對(duì)涵蓋整個(gè)系統(tǒng)的先進(jìn)處理器總線(xiàn)進(jìn)行分析作業(yè)。

在線(xiàn)仿真器的基本思想是提供一面通向嵌入式系統(tǒng)內(nèi)部的窗戶(hù)。程序員用線(xiàn)上仿真器將程序下載到系統(tǒng)運(yùn)行后, 可以對(duì)程序進(jìn)行逐步跟蹤并察看數(shù)據(jù)的變化。

之所以被叫做仿真器, 因?yàn)樗鼈兘?jīng)常用來(lái)模擬嵌入式系統(tǒng)中的中央處理器。通常來(lái)說(shuō), 它通過(guò)一個(gè)插頭插在一個(gè)與 CPU 一樣的底座上。由于是模擬主處理器, 仿真器可以在程序員的控制下做任何處理器可以做的操作。

在線(xiàn)仿真器總是將待開(kāi)發(fā)的嵌入式系統(tǒng)連接到一個(gè)終端或個(gè)人計(jì)算機(jī)。該終端或個(gè)人計(jì)算機(jī)為程序員調(diào)試和控制系統(tǒng)提供一個(gè)交互式的用戶(hù)界面。

值得注意的是，當(dāng)程序出現(xiàn)問(wèn)題，大多數(shù)的嵌入式系統(tǒng)會(huì)立刻變成毫無(wú)用處的廢銅爛鐵。嵌入式系統(tǒng)總是缺乏監(jiān)測(cè)軟件問(wèn)題的機(jī)制，比如內(nèi)存管理單元讀取緩存失敗等。如果沒(méi)有在線(xiàn)仿真器，嵌入式系統(tǒng)開(kāi)發(fā)將變得非常困難，因?yàn)楦緵](méi)有辦法知道究竟發(fā)生了什么問(wèn)題。而有了在線(xiàn)仿真器，程序員可以測(cè)試每一行源代碼，從而找到究竟是哪一段程序出錯(cuò)并糾正錯(cuò)誤以解決問(wèn)題。

在實(shí)際應(yīng)用中，程序員可以通過(guò)在線(xiàn)仿真器設(shè)置斷點(diǎn)、顯示和監(jiān)視內(nèi)存內(nèi)容以及控制輸入輸出。除此之外，程序員還可以通過(guò)在線(xiàn)仿真器設(shè)置各種條件斷點(diǎn)，從而有機(jī)會(huì)找到很多錯(cuò)誤的根源。

最近的一些在線(xiàn)仿真器不再因?yàn)榉抡娑枰粋€(gè)特殊的目標(biāo)系統(tǒng),而是利用由微控制器生產(chǎn)商提供的仿真和調(diào)試資源。雖然這樣的在線(xiàn)仿真器本身由于只處理微處理上的仿真電路, 而不是真正去模擬微處理器從而成本得到降低, 代價(jià)是在微處理器的設(shè)計(jì)過(guò)程中, 需要在保證提供足夠仿真機(jī)能的基礎(chǔ)上控制生產(chǎn)成本。

在線(xiàn)仿真器（英語(yǔ)：In-Circuit Emulator，簡(jiǎn)稱(chēng)：ICE）是調(diào)試嵌入式系統(tǒng)軟件的硬件設(shè)備。嵌入式系統(tǒng)開(kāi)發(fā)者要面對(duì)一般軟件開(kāi)發(fā)者所沒(méi)有的特殊問(wèn)題，因?yàn)榍度胧较到y(tǒng)往往不像商業(yè)計(jì)算機(jī)那樣具有鍵盤(pán)、顯示屏、磁盤(pán)機(jī)和其他各種有效的用戶(hù)界面和存儲(chǔ)設(shè)備。在線(xiàn)仿真器通過(guò)處理器的額外輔助功能，使系統(tǒng)在不失去其功能的情況下，提供調(diào)試功能。歷史上，由于處理器能力有限，這通常意味著將其處理器臨時(shí)更換成一個(gè)硬件仿真器。硬件仿真器是普通處理器的特制版本，內(nèi)部設(shè)有多種額外的調(diào)試信號(hào)，以便提供處理器內(nèi)部狀態(tài)的信息。

而現(xiàn)今，在線(xiàn)仿真器也可以指在處理器上直接進(jìn)行調(diào)試的硬件設(shè)備。由于JTAG等新技術(shù)的出現(xiàn)，人們可以直接在標(biāo)準(zhǔn)的量產(chǎn)型處理器上直接進(jìn)行調(diào)試，而不需要特制的處理器，從而消除了開(kāi)發(fā)環(huán)境與運(yùn)行環(huán)境的區(qū)別，也促進(jìn)了這項(xiàng)技術(shù)的低成本化與普及化。在這種情況下，由于實(shí)際上并沒(méi)有任何的“仿真”，“在線(xiàn)仿真器”是個(gè)名不副實(shí)的誤稱(chēng)，有時(shí)會(huì)造成一些誤解。當(dāng)仿真器被插入到待開(kāi)發(fā)芯片的某個(gè)部分的時(shí)候，在線(xiàn)仿真也被稱(chēng)作硬件仿真。這樣的在線(xiàn)仿真器，可以在系統(tǒng)運(yùn)行實(shí)時(shí)數(shù)據(jù)的情況下，提供相對(duì)很好的調(diào)試能力。

幾乎所有的嵌入式系統(tǒng)都由相互獨(dú)立但又相互依賴(lài)的硬件和軟件組成。通過(guò)在線(xiàn)仿真器，可以在軟件真正將要運(yùn)行的硬件上運(yùn)行和調(diào)試。同時(shí)，通過(guò)原碼級(jí)調(diào)試（Source Level Debug, 程序員可以看到運(yùn)行的源代碼）和單步調(diào)試（程序員可以一步一步的運(yùn)行程序?qū)ふ义e(cuò)誤），程序員可以方便的分離出錯(cuò)誤代碼。

大多數(shù)在線(xiàn)仿真器都由一個(gè)位于主機(jī)和被調(diào)試系統(tǒng)之間的適配器組成。接頭和電纜組件將適配器連接到待調(diào)試系統(tǒng)上用于安插微處理器的底座。而最近的在線(xiàn)仿真器上, 程序員可以通過(guò)JTAG或BDM接口連接到位于微處理器片上的調(diào)試 (On-Chip Debug) 電路進(jìn)行軟件調(diào)試。

由于在線(xiàn)仿真器模擬處理器, 所以在待調(diào)試系統(tǒng)看來(lái), 就像一個(gè)真的處理器；但從程序員角度看來(lái), 待測(cè)試系統(tǒng)能夠被完全控制, 可以直接下載、調(diào)試代碼等等。

大多數(shù)主機(jī)都是普通的與被開(kāi)發(fā)系統(tǒng)無(wú)關(guān)的商業(yè)計(jì)算機(jī)。例如: 安裝Windows系統(tǒng)的個(gè)人計(jì)算機(jī)可能被用來(lái)開(kāi)發(fā)在Freescale的 68HC11 系列微控制器上使用的軟件, 而 68HC11 本身并不能運(yùn)行 Windows 系統(tǒng)。

程序員一般在主機(jī)上編寫(xiě)和編譯嵌入式系統(tǒng)的代碼。所以主機(jī)上需要能為特定的嵌入式系統(tǒng)產(chǎn)生代碼的編譯器，他們被叫做交叉編譯器或匯編器。